
`include "ripple_carry_counter.v"

module stimilus();
	reg clk;
	reg reset;
	wire [3:0] q;
	
	ripple_carry_counter rcc(.clk(clk), .reset(reset), .q_out(q));
	
	// generate clock
	initial
		clk = 1'b0;
	always
		#5 clk = ~clk;
	
	initial begin
		$dumpfile("test.vcd"); //for gtkwave
		$dumpvars(0,rcc); //for gtkwave
		reset = 1'b1;
		#50 reset = 1'b0;
		#200 $finish;
	end
	
	initial
		$monitor($time, " Output q = %d", q);

endmodule